Co-design of Machine Learning Architecture and Hardware for Embedded Systems: Over the past few years, deep learning has helped forge advances in many different areas as diverse as image classification, machine translation, and voice recognition - all research topics that have long been difficult for AI researchers to crack. A subcategory of machine learning, deep learning deals with the use of neural networks to learn features automatically than writing handcrafted programs. This has become possible because computers become faster than it was a decade before. Most deep learning models are massive and take a long time to train. Currently, researchers use multiple high-end GPUs to train and infer such networks. Considering its potential in the future, it would be very beneficial if we can deploy deep nets (CNN, RNN, LSTM etc.) on embedded platforms. But, the large and complex network models work against the small silicon footprint and very limited power budget required for portable computers, tablets, and smartphones. My research interests lie in understanding the behavior of these complex models, optimizing them, and development of novel low power compute accelerator architectures that can support running them efficiently. My approach heavily involves cross-layer optimization across the stack - from model, implementation to underlying hardware architecture. I also aim at solutions which are mathematically guided and have a solid reasoning.